The Complete FPGA & RTL Interview Preparation Roadmap
Most candidates walk into an FPGA or RTL design interview unsure of what they will be asked. This roadmap removes that uncertainty: it is the complete map of what digital design interviews actually test, organized into eight modules - from digital logic fundamentals to timing closure and the design problems that separate strong candidates from the rest. Built from two decades of designing high-speed FPGAs and sitting on both sides of the interview table.
CoreAsked almost every timeDigital Logic · HDLs · Clocking & Timing · Design Problems
CommonFrequently askedFPGA Architecture · Communication Protocols · Verification & Debugging
SeniorDepth & differentiationAdvanced Topics & Applications
01Digital Logic FundamentalsCore
The essential building blocks of digital circuits.
Boolean Algebra & Logic Gates
- Basic gates (AND, OR, NOT, XOR, XNOR, NAND, NOR) and truth tables
- Boolean identities and simplification (K-Maps, Quine-McCluskey)
- SOP (Sum of Products) and POS (Product of Sums) forms
Combinational Logic Design
- Multiplexers (MUX) and Demultiplexers (DEMUX)
- Encoders and Decoders
- Adders (Half, Full, Ripple-Carry, Carry-Lookahead)
- Comparators; Shifters and Rotators
Sequential Logic Design
- Latches vs. Flip-Flops (SR, D, JK, T)
- Setup time, Hold time, Clock-to-Q, Propagation delay
- Synchronous vs. Asynchronous circuits
- Registers and Shift Registers (SISO, SIPO, PISO, PIPO)
- Counters (Synchronous, Asynchronous, Up/Down, Ring, Johnson)
Finite State Machines (FSMs)
- Mealy vs. Moore machines
- State diagrams and transition tables
- State encoding (Binary, One-hot, Gray)
- Common FSMs (sequence detectors, traffic-light controllers)
02Hardware Description Languages (Verilog / SystemVerilog / VHDL)Core
Practical use of HDLs to describe hardware - the cornerstone of RTL design.
HDL Basics
- Syntax and structure (modules/entities, architectures)
- Data types (wire, reg, logic, bit, std_logic, integer, real, arrays)
- Operators (arithmetic, logical, bitwise, relational)
- Concurrent vs. sequential statements (assign vs. always/process)
SystemVerilog Enhancements
- logic data type and its advantages over reg/wire
- typedef and enum for readability and type safety
- package for grouping common definitions
- Interfaces and modport (signal bundling, master/slave directionality)
- dot-star (.*) port mapping - usage, advantages, pitfalls
Behavioral & Structural Modeling
- always / process blocks and sensitivity lists
- Blocking vs. non-blocking assignments
- Conditionals (if-else, case/casez/casex) and loops
- Functions and Tasks
- Module instantiation, port mapping, hierarchical design
Common RTL Design Practices
- Inferring logic (latches, flip-flops, memories, FSMs)
- Parameterization and generics for reusable IP
- Reset methodologies (synchronous vs. asynchronous)
- Writing synthesizable RTL; FPGA coding-style guidelines
03FPGA Architecture and Design FlowCommon
Understanding the target hardware and the design process.
FPGA Architecture
- CLBs / Logic Elements: LUTs, flip-flops
- LUT-based shift registers (SRL16, SRL32)
- Routing resources and programmable interconnects
- Dedicated blocks: BRAMs, DSP slices, SerDes, PLLs/DCMs/MMCMs
- I/O blocks (IOBs); clocking resources (global clocks, clock trees)
Advanced Device Architectures
- SSI / multi-SLR devices (Super Logic Regions) and their implications
- SoC FPGAs (Zynq, Arria 10 SoC): Processing System vs. Programmable Logic
- MPSoC and RFSoC awareness; PS-PL communication (AXI, GPIO)
FPGA Design Flow
- Specification and design entry
- Synthesis: purpose, gate-level netlist, reports
- Implementation (Place & Route): mapping, placing, routing
- Floorplanning & Pblocks; bitstream generation and programming
Context
- FPGA vs. ASIC: key differences, advantages, disadvantages
- Vendors (Xilinx, Intel/Altera, Lattice, Microchip) and tools
04Clocking and Timing AnalysisCore
A critical area and a frequent interview topic - timing closure is paramount.
Clocking Concepts
- Frequency, period, duty cycle; clock skew and jitter
- Global vs. local clocks; generation/management (PLLs, DCMs, MMCMs)
- Clock fanout; inter-SLR clocking and routing
Static Timing Analysis (STA)
- Timing paths (reg-to-reg, input-to-reg, reg-to-output, input-to-output)
- Path delay (logic + routing); setup/hold; critical-path analysis
- Slack (positive vs. negative)
Timing Constraints (SDC)
- create_clock, create_generated_clock
- set_input_delay, set_output_delay
- set_false_path, set_max_delay/set_min_delay, set_multicycle_path
- Interpreting timing reports and exceptions
Timing Closure Techniques
- RTL: pipelining (and latency trade-offs), retiming, parallelism
- Reducing levels of logic; managing high-fanout nets; using BRAMs/DSPs/SRLs
- FSM encoding (one-hot for speed, binary for area)
- Tool directives (DONT_TOUCH, MAX_FANOUT, RAM_STYLE, ASYNC_REG)
- Physical constraints (floorplanning, Pblocks, LOC); failing-path analysis
Clock Domain Crossing (CDC)
- Metastability and its implications
- Synchronizers (double/multi-flop), async FIFOs, handshake protocols
- CDC linting and verification
05Communication ProtocolsCommon
On-chip and off-chip protocols for integrating IP and external devices.
AXI (Advanced eXtensible Interface) Family
- AXI4 (Full): memory-mapped; channels; bursts (INCR, WRAP, FIXED); VALID/READY
- AXI4-Lite: simple control/status registers; no burst support
- AXI4-Stream: streaming; TVALID/TREADY/TDATA/TLAST/TKEEP/TSTRB; packet-based
Serial Buses
- I2C: two-wire multi-master; SDA/SCL; start/stop, addressing, ACK/NACK
- SPI: four-wire full-duplex; SCLK/MOSI/MISO/SS; CPOL/CPHA modes
- Protocol comparison: speed, complexity, pin count, multi-master
06Verification and DebuggingCommon
Methodologies for functional correctness, plus debugging real hardware.
Simulation & Testbench Development
- Event-driven simulation and simulators (ModelSim, QuestaSim, XSim, VCS)
- Testbench structure, stimulus generation, response checking
- Self-checking testbenches, file I/O, waveform analysis
Verification Methodologies
- Functional verification; code coverage (line, branch, FSM, toggle)
- Assertion-based verification (SystemVerilog Assertions)
- Introduction to UVM (awareness)
On-Chip Debugging
- Integrated Logic Analyzers (ILAs): concept, resource use, vs. sim
- Vendor tools (Vivado ILA, SignalTap): triggering, depth, mark_debug
- Virtual I/O (VIO) cores for interactive control/monitoring
Debugging Strategies
- Incremental debugging; debug registers, status flags, counters
- Observing FSM states; handling FIFO under/overflow
- JTAG & boundary scan; when to reach for lab equipment
07Advanced Topics & ApplicationsSenior
Topics that demonstrate deeper understanding and real experience.
Specialized Areas
- Memory interfaces: SDRAM, DDR/2/3/4 (controllers and PHY)
- DSP on FPGAs: fixed vs. floating point, FIR filters, FFT, DSP slices
- High-Level Synthesis (HLS): C/C++ to RTL, pros/cons, applications
Engineering Practice
- Scripting: Tcl (Vivado, Quartus); Python (testbench gen, ChipScoPy)
- Design for Testability: scan chains, boundary scan (JTAG)
- Common challenges: resource/power optimization, throughput vs. latency
08Common Design & Coding ProblemsCore
The RTL problems used in interviews to test practical coding and judgment.
Counters & Data Path
- Divide-by-N counter (e.g., divide-by-3 with 50% duty cycle)
- Barrel shifter; priority encoder/decoder; generic comparators/adders
Converters & Synchronization
- Binary-to-Gray and Gray-to-Binary converters; BCD to 7-segment
- Button debouncer; edge detectors (rising, falling, both)
Memory, FIFOs & Arbitration
- Synchronous FIFO controller (pointers, full/empty flags)
- Skid buffer for pipelined back-pressure; simple memory controller
- Arbiters: round-robin and priority
Modules & Algorithms
- UART receiver/transmitter (simplified)
- FSM applications: traffic-light controller, sequence detector
- GCD (Euclidean algorithm); PWM generator
Want it all sequenced for you?
This roadmap shows you what to master. Demystifying the Digital Design Interview shows you why — the design intuition, the trade-offs, and the judgment behind every topic here, with 200+ embedded questions drawn from 20 years in industry.
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