Why Only the D Flip-Flop Exists as an FPGA Primitive
You studied four types of flip-flops in school. Only one survived into modern FPGAs — and the reason comes down to forbidden states, feedback topology, and what Static Timing Analysis needs to do its job.
You studied RS, JK, T, and D flip-flops in school. So why is only one of them available as a primitive in modern FPGAs?
This is a question that trips up a surprising number of engineers in interviews — even experienced ones. The knee-jerk answer is usually something vague about "the D flip-flop being simpler." That's not wrong, but it misses the real story. The answer comes down to synthesis predictability, feedback topology, and what Static Timing Analysis actually needs to do its job.
A Brief History Worth Knowing
These flip-flops weren't just academic constructs. The JK flip-flop — the 7476 in the 7400 TTL series — was a real chip. Engineers wired them up on breadboards. They appeared in lab kits for decades. The idea that only the D flip-flop survived into the FPGA era isn't obvious if you only learned about them from a textbook. Each type was once genuinely useful.
So what happened?
The RS Flip-Flop: A Forbidden State Problem
The RS (or SR) flip-flop has four input combinations: S=0/R=0, S=1/R=0, S=0/R=1, and S=1/R=1.
The first three are fine. S=1/R=1 is the problem — it produces an indeterminate output. Both Q and Q̄ go high, which is already a contradiction (they should be complementary), and the output when the inputs return to 0 is unpredictable. It depends on which signal transitions first.
For a synthesis tool, "indeterminate output" is unworkable. The tool needs to map your RTL to hardware and make guarantees about that hardware's behavior. A primitive with a forbidden state — one where the output is undefined — cannot participate in that guarantee. You'd have to add external gating to ensure S=1/R=1 never occurs, and at that point you're no longer describing the RS flip-flop, you're describing something else.
The RS flip-flop does have legitimate uses in specific asynchronous applications (debounce circuits, for instance — see Chapter 6 of Demystifying the Digital Design Interview), but those use the flip-flop at the gate level, not as an inferred sequential element in RTL synthesis.