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Milind Parelkar

Milind Parelkar

Principal Engineer/Manager, Qualcomm

📍 California

Design Question: Counter that Skips Every Multiple of 3

Design a counter that starts at 1 and outputs a new value on every clock cycle, but it must never output a multiple of 3. The sequence looks like this: 1, 2, 4, 5, 7, 8, 10, 11, 13, 14 … — every third number is skipped. When most students first see

The Complete FPGA & RTL Interview Preparation Roadmap

Most candidates walk into an FPGA or RTL design interview unsure of what they will be asked. This roadmap removes that uncertainty: it is the complete map of what digital design interviews actually test, organized into eight modules - from digital logic fundamentals to timing closure and the design problems that