Start here
fpgadesign.io is a concept-first resource for engineers preparing for RTL, ASIC, and FPGA design interviews. The goal isn't to memorize answers ā it's to understand the why behind design decisions so you can reason through anything an interviewer throws at you.
Pick your starting point
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New grad / early career
Start with Digital Logic to build the foundation, then move to SystemVerilog. Read the blog articles alongside the question banks ā the concepts reinforce each other.
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Experienced engineer refreshing
Go straight to FPGA Architecture or Design Questions. The advanced blog articles on CDC, STA, and AXI are worth reading too.
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Switching from software or verification
Start with the SystemVerilog bank to understand RTL thinking, then use the blog articles to fill gaps in hardware fundamentals.
The free question banks
All four question banks are free. No account needed ā just bookmark what's useful.
Digital Logic
Combinational, sequential, arithmetic, FSMs
SystemVerilog
RTL design, blocking vs non-blocking, interfaces
FPGA Architecture
CLBs, LUTs, BRAM, clocking, timing
Design Questions
Applied RTL ā arbiters, FIFOs, barrel shifters
Want a structured path?
Demystifying the Digital Design Interview
If you want all of this sequenced for you ā with 200+ embedded questions and author's notes from 20 years of industry experience ā the book covers it end to end. Available on Amazon in paperback, hardcover, and Kindle.
View book details ā
Questions? Reach out at milind@fpgadesign.io or on LinkedIn.