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Design Questions

Basic — single-concept designs
Intermediate — multi-cycle & sequential
Advanced — interface & system-level
RTL design questions test your ability to translate a spec into synthesizable hardware. Focus on getting the architecture right first — then think about edge cases, reset behavior, and timing.

Basic Questions

Basic 6 questions
1

Design a module to generate a pulse once every 32 clock cycles. Extra credit for a design optimized for Xilinx FPGA architecture.

Counters Read Answer →
2

Design a divide-by-2 module to divide the input clock.

Clock Dividers Read Answer →
3

Design a divide-by-3 module to divide the input clock.

Clock Dividers Read Answer →
4

Design a divide-by-3 module to divide the input clock. The generated output signal must have a 50% duty cycle.

Clock Dividers Read Answer →
5

Design a Binary to Gray Code converter.

Data Converters Read Answer →
6

Design a module to detect Odd Parity. The module receives a single bit serial input. The output shall be asserted when the number of 1s received is odd.

Sequence Detectors Read Answer →

Intermediate Questions

Intermediate 6 questions
1

Design a sequence detector to detect the following sequence: 0, 1, 1, 1, 0, 0.

Sequence Detectors Answer in Book →
2

Design a 4-bit Full Adder based on a 1-bit Full Adder module provided to you. The design must be completely pipelined at the boundaries of the 1-bit Full Adder module.

Arithmetic Answer in Book →
3

Design a 4-bit × 4-bit multiplier using a memory.

Arithmetic Answer in Book →
4

Design a 4-bit Gray Code counter.

Counters Answer in Book →
5

Design a counter module that gets initialized to 1 on reset. The counter should count up and skip every multiple of 3. Every output value should remain on the output bus for a single clock cycle.

Counters Answer in Book →
6

Design an UP-DOWN Counter that counts from 4 to 14, based on a select input up_down.

Counters Read Answer →

Advanced Questions

Advanced 6 questions
1

Design a skid buffer to handle Ready-Valid handshaking. Extra credit for Xilinx FPGA architecture design alternatives.

Interface Design Answer in Book →
2

Design an 8-bit Parallel-to-Serial Converter. The module receives 8-bits of data per clock cycle, with 16 dead cycles between consecutive data words. The module has a single-bit serial output.

Shift Registers Answer in Book →
3

Design a module that receives a single bit serial input (dat) qualified with a vld signal. The module should detect the stream marker sequence — 1, 1, 1, 0, 0, 0 — and output the 4 bits that preceded the stream marker.

Sequence Detectors Answer in Book →
4

Design a data distributor module that receives a single 8-bit data word per clock cycle qualified with a vld signal. The module distributes data words to 4 outputs in a circular fashion.

Interface Design Answer in Book →
5

Design a module that will generate the following sequence of decimal numbers — 3, 11, 29, 47, 55, 62 — and then roll over to keep generating the same sequence.

Counters Answer in Book →
6

AXI-Streaming interfaces have a TLAST signal to indicate the end of a packet. Design a module to take an incoming AXI-Streaming interface and add Start-of-Packet (SOP) and End-of-Packet (EOP) markers to the interface.

AXI Answer in Book →

Want detailed answers with full explanations?

All questions are covered in depth in the book — with context, design rationale, and follow-up discussion.

View the Book →