By Milind Parelkar in newsletter — 28 Jun 2026

fpgadesign.io #1: Setup & Hold, and Why One is Scarier

Welcome to the first issue of the fpgadesign.io newsletter — or, for some of you, welcome back.

A while ago I ran a newsletter on Substack, but a number of constraints meant I had to put it on hold. Now that the book is finally out, I'm restarting it — this time on my own platform at fpgadesign.io, where I have the room to do it the way I want.

Since the book came out, I've been hearing from students and engineers prepping for RTL and FPGA interviews, and the same questions keep coming up.

So every two weeks I'll take one concept interviewers love to probe and explain it the way I wish someone had explained it to me when I was starting out — plus a real interview question, a design problem, and what's worth your attention in the field.

Let's start with a topic, where a lot of careers get made or broken: timing closure.

⚡ Concept Focus: Setup and hold, and why one is scarier

A flip-flop can't capture data at the exact instant the clock edge arrives — it needs the data stable for a small window around the edge. Setup time is how long data must be stable before the edge; hold time is how long it must stay stable after.

Here's the part that matters in interviews and on the device.

A setup check is a longest-path problem — if your slowest path can't make it in one clock period, you fail setup, and you can always slow the clock down to fix it (or pipeline, reduce logic levels, retime).

Setup:  T_clk >= t_cq + t_comb(max) + t_su     (longest path)
Hold:   t_cq + t_comb(min) >= t_h              (shortest path - no T_clk!)

A hold check is a shortest-path problem. Notice what's missing: the clock period. Hold has nothing to do with frequency. A chip that fails hold is broken at any speed — you can't slow your way out. The fix is adding delay to the fast path, and the usual culprit is clock skew.

So when someone asks "which is worse?" — hold. A setup failure is a performance limit; a hold failure is a functional one.

🎯 Interview question

Q: "What's the difference between a setup violation and a hold violation — and if you could only have one, which would you rather see in your timing report?"

How to approach it: define both in terms of the data-stability window, then land the key insight — setup scales with the clock period (slow the clock and it's fixable), hold doesn't (broken at any frequency, usually skew). You'd rather have a setup violation. (This is explained in detail in Chapter 4 of the book.)

🧩 Design question

Design a sequence generator that starts at 1 after reset and outputs an incrementing sequence every clock — but never outputs a multiple of 7.
So: 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 15, …
Each value appears for exactly one cycle.
How would you build it?
Did you approach this at the gate level, RTL level, structural level or with waveforms?

Give it a shot. If anything about the problem statement is unclear — or you'd like to talk through your approach — just reply. I read every email and I'm happy to help.

Hint: I already have a blog post about a counter that skips every multiple of 3.

🛠 Author's note

Logical and routing delays: A rule of thumb is that the routing delay should generally not consume more than 60% of the clock period for efficient routing and timing closure in FPGA designs.

📌 Latest from fpgadesign.io

On the blog — three timing reads to go deeper:

Reading a Timing Report: Why Your First Instinct Might Be Wrong — most engineers see a violation and reach for pipelining. The report already tells you the fix, once you read the logic-vs-route split.

Negative Hold Time Values in the Datasheet — a perfect companion to today's issue: why hold times can go negative, and what that buys you for timing closure.

"Levels of Logic" in FPGA Timing Reports — what that number really means, and why it's often the first thing to check when a path won't close.

📌 ICYMI on LinkedIn

A 3-part series on using AI for SystemVerilog & RTL:

Part 1 — Do you use AI to write SystemVerilog? — the unlock isn't the model; it's feeding it your own golden modules so it writes in your style, not generic RTL.

Part 2 — Not every hour of engineering is engineering — where AI shines: the mechanical-but-well-specified work (bus hookups, dead-code sweeps, XDC sync). Prep the field; AI executes.

Part 3 — Where human expertise is still irreplaceable — the failure modes: false CDC, reinvented components, package vs. localparam, pipeline balance. AI writes code; engineers design systems.

🔗 Worth reading

AMD UltraFast Design Methodology Guide (UG949) — the timing-closure chapter is the best free reference on closing timing in Vivado.

💬 Reader mailbag

New issue, so let's start one: what interview topic do you find hardest, and why? Just hit reply — I read every one, and your answers shape future issues.

📡 On the radar

AMD launched Kintex UltraScale+ Gen 2 mid-range FPGAs (up to 5x memory bandwidth, 2x PCIe channel density).

AMD's Versal Prime Series Gen 2 added smaller embedded-class devices — the PS-PL partitioning question keeps getting more important; know where your logic should live.

Altera is now an independent company again.

📘 Before you go

If this was useful, forward it to one engineer who's prepping for interviews — that's how this grows. And if you have a question, or want to talk through this issue's design problem, just reply — it comes straight to my inbox.

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