fpgadesign.io #2 — The Shift that Costs Zero Logic Levels
fpgadesign.io — Issue #2
RTL & FPGA design, explained the way interviews actually test it.
👋 Welcome back.
Last issue: timing. Setup, hold, and why a hold violation is the one that should scare you. Several of you replied with your attempts at the skip-3 counter. Exactly what I hoped