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Design Questions

A collection of 6 issues

Design Question: Counter that Skips Every Multiple of 3

Design a counter that starts at 1 and outputs a new value on every clock cycle, but it must never output a multiple of 3. The sequence looks like this: 1, 2, 4, 5, 7, 8, 10, 11, 13, 14 … — every third number is skipped. When most students first see

Design Question - Odd Parity Detector

How does Parity ensure data integrity? What are its limitations? Concept, Design Choices, FSM explained with SystemVerilog code

Design Question - Up-Down Counter with a Twist

Design Details, Explanation and Complete SystemVerilog RTL

Design Question - Barrel Shifter

What is a Barrel Shifter? How does it compare to a Shift Register? All concepts explained along with the SystemVerilog code for a 4-bit Barrel Shifter.

Design Question - Clock Dividers and Duty Cycle

The ubiquitous Divide-by-3 Counter with 50% Duty Cycle and its siblings.

Design Question - Pulse Generator

You are asked to design a module that generates a pulse, once every 32 clocks. How many ways can you implement the design? Would you do anything different if you are targeting a Xilinx UltraScale+ FPGA?