Control Sets Demystified
What are Control Sets in an FPGA Design? How do they affect the QoR of the final Placed and Routed Design?
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Design Question - Pulse Generator
You are asked to design a module that generates a pulse, once every 32 clocks. How many ways can you implement the design? Would you do anything different if you are targeting a Xilinx UltraScale+ FPGA?
Rethinking Resets: Best Practices for FPGA Design
While designing an RTL module, most engineers do not even give a second thought to the reset signal. Every textbook on the subject touches upon the pros and cons of synchronous vs asynchronous resets. The texts generally focus on the correct syntax for inferring a synchronous or an asynchronous reset.