~ vs ! in SystemVerilog: The Bug the Compiler Won't Catch
On a single-bit signal, ~ and ! give the same result. On a multi-bit signal, they can give opposite answers — and the compiler won't warn you.
Topic
SystemVerilog
A collection of 4 issues
Packed vs Unpacked Arrays in SystemVerilog
Concepts, Use Cases, Syntax and Synthesis Considerations for using Packed vs Unpacked arrays in SystemVerilog
SystemVerilog .name and .* Notations
Do you use the .name and .* constructs in SystemVerilog? The advantages of using them and some more thoughts about streamlining your code.
Intricacies of Blocking vs Non-Blocking Assignment Statements in SystemVerilog
Have you really understood the nuances of Blocking vs Non-Blocking Assignment statements in SystemVerilog?