Packed vs Unpacked Arrays in SystemVerilog

SystemVerilog provides powerful enhancements over Verilog, particularly in handling arrays. Among these, packed and unpacked arrays play a crucial role in designing efficient hardware descriptions. While both serve distinct purposes, understanding their differences is essential for writing optimized and maintainable RTL code.

SystemVerilog refers to the legacy Verilog array declaration style as unpacked arrays. Each element of an unpacked array may be stored independently from other elements, but grouped under a common name.

Vector declarations are referred to as packed arrays in SystemVerilog. The entire packed array must be stored as contiguous bits, without any padding.

SystemVerilog Syntax

The array dimensions are specified after the signal name for unpacked arrays, and before the signal name for packed arrays. It is also possible to have a mix of packed and unpacked dimensions within the same array declaration.

logic         data_in [31: 0];  // unpacked array
logic         data_in [32];     // unpacked array (C-style declaration)
logic [31: 0] data_in;          // packed   array

Use Cases for Array Types

Packed Arrays

Packed arrays are ideal for situations where bit manipulations need to be performed or bit-slices need to be referenced.