ASIC-Style Clock Gating in FPGAs
How does ASIC-style Clock Gating translate to FPGA prototypes?
Milind Parelkar
Understanding Clock Constrains
A complete overview starting with the basic timing constraints and building it up to the more advanced categories.
IOSTANDARDs in Xilinx FPGAs
What are they and Why are they needed in FPGA Design?
Endianness: The Byte Order You Didn't Know You Needed to Know
Most engineers writing high-level software don't even care, but if you are engaged in low-level debugging at the hardware level, you definitely need to be aware of the the data "endianness" and how to handle it.
Design Question - Odd Parity Detector
How does Parity ensure data integrity? What are its limitations? Concept, Design Choices, FSM explained with SystemVerilog code
Design Question - Up-Down Counter with a Twist
Design Details, Explanation and Complete SystemVerilog RTL
Tri-State Buffers and Their Applications
How do complex microprocessor systems preserve the integrity of data buses?
Mealy and Moore Finite State Machines (FSMs)
Key Differences and Synthesis Implications
Packed vs Unpacked Arrays in SystemVerilog
Concepts, Use Cases, Syntax and Synthesis Considerations for using Packed vs Unpacked arrays in SystemVerilog
Design Question - Barrel Shifter
What is a Barrel Shifter? How does it compare to a Shift Register? All concepts explained along with the SystemVerilog code for a 4-bit Barrel Shifter.