An Introduction to Xilinx FPGA Memory Primitives
Practical Insights into BlockRAM, Distributed RAM, and UltraRAM usage in your designs.
Topic
FPGA Concepts
A collection of 13 issues
Control Sets Demystified
What are Control Sets in an FPGA Design? How do they affect the QoR of the final Placed and Routed Design?
Rethinking Resets: Best Practices for FPGA Design
While designing an RTL module, most engineers do not even give a second thought to the reset signal. Every textbook on the subject touches upon the pros and cons of synchronous vs asynchronous resets. The texts generally focus on the correct syntax for inferring a synchronous or an asynchronous reset.