Understanding Synthesis Directives
Optimize your SystemVerilog RTL design for quality of synthesis results! Learn how synthesis directives (attributes) like KEEP and DONT_TOUCH provide crucial hints to your tools, enabling advanced optimization, timing closure, and efficient resource utilization in hardware design.
As hardware designers, we write RTL (Register-Transfer Level) code in languages like SystemVerilog to describe the behavior of our digital circuits. But between that descriptive code and the final bitstream, there's a crucial step: synthesis. Synthesis tools interpret our SystemVerilog RTL and map it to the actual gates and primitives available on our target FPGA or ASIC.
This is where synthesis directives, also known as synthesis attributes or pragmas, come into play. They are special constructs embedded directly in your SystemVerilog code that serve as explicit instructions or "hints" to the synthesis tool, guiding its optimization process beyond what it could infer purely from standard HDL. Some of these are "soft" directives, which are used to point the tool in the direction that the designer is leaning towards, but the final decision rests with the tool. "Hard" directives on the other hand override any decisions that the tool might make otherwise.
What are SystemVerilog Synthesis Directives?
SystemVerilog synthesis directives are not part of the core IEEE standard for the language. Instead, they are vendor-specific or tool-specific meta-information that you embed directly into your code. They do not affect the simulation behavior of your RTL, but they significantly influence the output of the synthesis stage.
SystemVerilog Syntax Example:
In SystemVerilog (and Verilog), directives are typically placed as (* attribute_name = "value" *) right before the declaration of a module, wire, logic signal, register, or instanced component. Some are also inline comments like // synthesis translate_off.