Control Sets Demystified

A control set is a group of control signals (set/reset, clock enable, and clock) that drives any given SRL, LUTRAM, or register. Each unique combination of these signals forms a different control set.

Let’s break it down with an example: Imagine you have two registers, A and B, both driven by the same clock. If register A needs a clock enable but register B doesn’t, they end up in different control sets. This means they can’t be packed into the same CLB slice.

How Control Sets Affect Packing

The way control sets are packed depends on the FPGA architecture and device family:

• 7-Series Devices: A slice (or half a CLB) has eight registers. All registers in a slice share one clock, one set/reset, and one clock enable. So, only one control set can be used per group of eight registers.
• UltraScale Devices: Each half-CLB consists of two sets of four registers. Each set has its own clock, set/reset, and clock enable. Ideally, you can use two control sets per eight registers, allowing for tighter resource packing compared to the 7-series architecture.

Why Does This Matter?

Control set restrictions in CLB packing can make the placer shift some registers and their input LUTs around. Sometimes, these registers end up in less ideal spots. This extra distance can mess with utilization, placement quality, and power consumption because of longer net delays and more interconnect usage. This is especially a problem in designs with lots of low fanout control signals, like clock enables that only feed one register. In short, code written without any thought about optimizing for control sets, will usually result in wasted resources and potentially cause localized congestion due to the spread of logic.

Unused Control Signals and Constants

Unused inputs on a primitive don’t create new control sets. For example, if a PRESET on an FDRE primitive isn’t connected, it’s ignored and won’t create a new control set. Undriven reset signals can be tied off internally within a slice and won’t lead to a unique set either.

Tips for Designing and Coding

• Avoid different clock enables for logically related registers. For instance, if you have a data and control pipeline flowing in lock-step, don’t use different clock enables for these paths. This allows for more efficient logic packing.
• Avoid different set/reset signals for logically related registers.
• Don’t code always_ff blocks with a constant clock enable signal (set to 1) or a reset signal set to a constant. It is more optimal to avoid these constants in the always block.

Troubleshooting Control Set Issues in Vivado (Post-Synthesis)

• Check for unnecessary MAX_FANOUT attributes on control signals in the RTL and constraints. Replicating control signals can cause the number of control sets to blow up.
• Avoid asynchronous set/reset signals unless necessary. These can only be routed to dedicated asynchronous pins and can’t be absorbed into the datapath during synthesis.
• Don’t use both active high and active low versions of the same control signal for different sequential elements. This practice is generally frowned upon.
• Use clock enables and set/resets sparingly. Often, data paths contain many registers that automatically flush uninitialized values, where set/reset or enable signals are only needed on the first and last stages.

Related Interview Questions

• What is a control set in an FPGA?
• What factors affect the number of control sets in a design?
• How can the number of control sets in a design be minimized?
• What are the benefits of minimizing the number of control sets in a design?
• What are the drawbacks of using too many control sets?