Design Question - Barrel Shifter What is a Barrel Shifter? How does it compare to a Shift Register? All concepts explained along with the SystemVerilog code for a 4-bit Barrel Shifter.
Design Question - Clock Dividers and Duty Cycle The ubiquitous Divide-by-3 Counter with 50% Duty Cycle and its siblings.
Design Question - Pulse Generator You are asked to design a module that generates a pulse, once every 32 clocks. How many ways can you implement the design? Would you do anything different if you are targeting a Xilinx UltraScale+ FPGA?