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FPGA Concepts

Basic Questions

  1. What are some of the primitive elements inside an FPGA?
  2. What is the difference between an FPGA, a CPLD and a Microcontroller? What are the typical applications for each of these devices?
  3. What clocking blocks are available in a typical Xilinx FPGA?
  4. What are the different types of memory elements available inside a Xilinx UltraScale+ family of FPGAs? (Link to Answer)
  5. What are the most basic type of design constraints required for any FPGA design?
  6. What sort of debugging tools are available in the Xilinx Toolkit?
  7. ASIC Designs frequently use clock gating to turn off the clock to certain sections of the design. How is similar functionality handled on an FPGA?

Advanced Questions

  1. What does Stacked Silicon Interconnect (SSI) mean?
  2. What are Super Logic Regions (SLRs) in some Xilinx devices?
  3. What precautions need to be taken while using SSI devices or while handling signals crossing SLR boundaries?
  4. What are some of the considerations while using resets in Xilinx FPGA Designs? (Link to Answer)
  5. On a Xilinx UltraScale+ device, there are two pairs of differential clock inputs - one is a 400MHz clock coming in on a GC pin and the other is a 312.5 MHz MGTREFCLK. How can you generate the following clock frequencies for internal use - 50 MHz, 200 MHz, 156.25 MHz?
  6. What is Retiming? What are the typical scenarios where it might be useful?
  7. Two of the most common hinderances in Timing Closure are high-fanout nets and excessive levels of logic. How should either of these problems handled in the design?
  8. A register stores an 8-bit value. This has to be shifted left by 4 bit positions. How many levels of logic will be needed to implement this operation?
  9. What are Timing Exceptions? Why is it important to specify them?
  10. What are Synthesis Directives? Explain with some common examples.
  11. What is the difference between the directives, KEEP and DONT_TOUCH?
  12. What are XPMs (Xilinx Parameterizable Macros) and where are they typically used?
  13. What is Floorplanning? Explain the thought process and the steps in Floorplanning a design.
  14. Xilinx IP Library has FIFOs designated as First Word Fall Through(FWFT). Explain the design significance and use cases of these FIFOs.
  15. Xilinx Dual Port BlockRAMs have two flavors - Simple Dual Port and True Dual Port. What are the differences between the two types?
  16. A module implemented on a Xilinx FPGA needs to send out source synchronous data (along with the clock). How should the data and the clock be handled at the FPGA IOs?