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Design Questions

Question Bank of Digital Design and RTL Interview Questions

  1. Design a sequence detector to detect the following sequence -
    0, 1, 1, 1, 0, 0
  2. Design a module to generate a pulse once every 32 clock cycles.
    Extra credit for a design optimized for Xilinx FPGA architecture. (Link to Answer)
  3. Design a divide-by-2 module to divide the input clock. (Link to Answer)
  4. Design a divide-by-3 module to divide the input clock. (Link to Answer)
  5. Design a divide-by-3 module to divide the input clock. The generated output signal must have a 50% duty cycle. (Link to Answer)
  6. Design a Binary to Gray Code converter. (Link to Answer)
  7. Design a module to detect Odd Parity.
    The module receives a single bit serial input. The output of the module shall be asserted when the number of 1s received is an odd number. (Link to Answer)
  8. Design a skid buffer to handle Ready-Valid handshaking.
    Extra credit for Xilinx FPGA Architecture design alternatives.
  9. Design a 4-bit Full Adder, based on a 1-bit Full Adder module provided to you. The design must be completely pipelined at the boundaries of the 1-bit Full Adder module.
  10. Design a 4-bit x 4-bit multiplier using a memory.
  11. Design an 8-bit Parallel-to-Serial Converter.
    The module receives 8-bits of data per clock cycle, with 16 dead cycles between consecutive data words. The module has a single-bit serial output.
  12. Design a module that has the capability to receive a single bit serial input (dat), qualified with a vld signal. The module should detect the stream marker sequence - 1, 1, 1, 0, 0, 0 - and output the 4 bits that preceded the stream marker. For example, if the sequence is -
    0, 0, 1, 0, 1, 1, 1, 0, 0, 0, a, b, c, d . . ., the output of the module should be the 4-bits - a, b, c, d.
  13. Design a data distributor module that can receive a single 8-bit data word per clock cycle, qualified with a vld signal. The distributor module should have 4 outputs, each 8-bits wide. The module distributes the first data word it receives to Output Index 0, the next one to Output Index 1 and so on, in a circular fashion.
  14. Design a 4-bit Gray Code counter.
  15. Design a counter module that gets initialized to 1 (decimal) on reset. The counter should count up and skip every multiple of 3. Every output value should remain on the output bus for a single clock cycle.
  16. Design a module that will generate the following sequence of decimal numbers - 3, 11, 29, 47, 55, 62. The sequence generator should then roll over and keep generating the same sequence.
  17. Design an UP-DOWN Counter that counts from 4 to 14, based on a select input, up_down. (Link to Answer)
  18. AXI-Streaming interfaces have a TLAST signal to indicate the end of a packet. Design a module to take an incoming AXI-Streaming interface and add Start-of-Packet (SOP) and End-of-Packet (EOP) markers to the interface.