Packed vs Unpacked Arrays in SystemVerilog
Concepts, Use Cases, Syntax and Synthesis Considerations for using Packed vs Unpacked arrays in SystemVerilog
Milind Parelkar
Design Question - Barrel Shifter
What is a Barrel Shifter? How does it compare to a Shift Register? All concepts explained along with the SystemVerilog code for a 4-bit Barrel Shifter.
Advanced Topics in Static Timing Analysis
Understanding Clock Skew, Clock Jitter and effects of additional pipelining on latency.
The Fundamentals of Static Timing Analysis in Digital Circuits
Setup and Hold Time, Critical Paths and Other Key Concepts Explained
Design Question - Clock Dividers and Duty Cycle
The ubiquitous Divide-by-3 Counter with 50% Duty Cycle and its siblings.
SystemVerilog .name and .* Notations
Do you use the .name and .* constructs in SystemVerilog? The advantages of using them and some more thoughts about streamlining your code.
Intricacies of Blocking vs Non-Blocking Assignment Statements in SystemVerilog
Have you really understood the nuances of Blocking vs Non-Blocking Assignment statements in SystemVerilog?
Designing with Xilinx Memory Primitives: Understanding Inference vs Instantiation
When would you infer a memory primitive? What are the advantages of instantiating a memory module? There is a third alternative to inference vs instantiation. Do you know what it is?
An Introduction to Xilinx FPGA Memory Primitives
Practical Insights into BlockRAM, Distributed RAM, and UltraRAM usage in your designs.
Gray Codes and Their Uses in Digital Design
What are Gray Codes? Where are these codes used in Digital Design?