# fpgadesign.io
> RTL and FPGA design interview prep — concept-first articles, question banks, and a book that explains the why behind design decisions.
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Append `.md` to any post or page URL to get the content in Markdown (for example, `/example-post.md`).

## Pages
- [About](https://fpgadesign.io/about.md) - A few years ago, when the tech industry was going through a rough round of cuts and no one felt entirely untouchable, I set out to prepare for hardware engineering interviews. Twenty years of industry experience, and the resources available were, frankly, a mess. Multiple books covering the same gr…
- [Book Details](https://fpgadesign.io/book-details.md) - Demystifying the Digital Design Interview The Missing Guide for Practical RTL and FPGA Interview Preparation 200+ embedded interview questions. Concept-first structure. Real engineering insight from 20 years in the industry — not recycled textbook content. Order on Amazon → Paperback · Hardcover ·…
- [Book Preview](https://fpgadesign.io/book-preview.md)
- [Design Questions](https://fpgadesign.io/design-questions.md) - Basic — single-concept designs Intermediate — multi-cycle & sequential Advanced — interface & system-level RTL design questions test your ability to translate a spec into synthesizable hardware. Focus on getting the architecture right first — then think about edge cases, reset behavior, and timing.…
- [Digital Logic](https://fpgadesign.io/digital-logic.md) - Basic — foundational concepts Intermediate — applied understanding Advanced — depth & edge cases In RTL design interviews, you will often be asked to explain basic digital design concepts. Before diving into advanced sections, make sure your foundation is strong. Basic Questions Basic 8 questions 1…
- [FPGA Concepts](https://fpgadesign.io/fpga-concepts.md) - Basic — FPGA fundamentals Intermediate — architecture & timing Advanced — system-level & optimization FPGA interview questions test both your theoretical knowledge of the architecture and your practical experience with tools and constraints. Understanding the "why" behind design choices is what sep…
- [Home](https://fpgadesign.io/home.md) - Milind Parelkar High-Speed FPGA Design · Author Principal Engineer/Manager, Qualcomm Research Demystifying the Digital Design Interview The RTL and FPGA Interview Guide Built on 20 Years of Industry Experience 200+ interview questions. Concept-first structure. Real engineering insight — not recycle…
- [Newsletter](https://fpgadesign.io/newsletter.md) - fpgadesign.io The Newsletter RTL & FPGA design, explained the way interviews actually test it. Every other Sunday, one concept interviewers love to probe — taught the why-over-what way, with a real interview question, a build-it design problem, and what's worth your attention in the field. Free. No…
- [Start here](https://fpgadesign.io/start-here.md) - fpgadesign.io is a concept-first resource for engineers preparing for RTL, ASIC, and FPGA design interviews. The goal isn't to memorize answers — it's to understand the why behind design decisions so you can reason through anything an interviewer throws at you. 💡New to interview prep? Start with t…
- [SystemVerilog Questions](https://fpgadesign.io/sv-interview-questions.md) - Basic — foundational concepts Advanced — depth & edge cases In most RTL design interviews, you will be asked to write some code, or explain what a snippet does, or what it synthesizes to. Make sure your SystemVerilog fundamentals are solid before tackling advanced topics. Basic Questions Basic 5 qu…

## Posts
- [fpgadesign.io #4 - Clocks should be Handled with Extreme Care](https://fpgadesign.io/blog/fpgadesign-io-4-clocks-should-be-handled-with-extreme-care.md) - 👋 Welcome back. Last issue: reset. Assert asynchronously, de-assert synchronously — and one reset bridge per clock domain, not one global reset trying to serve them all. A few of you wrote back with reset bugs that had been hiding in the lab for months. Keep them coming. This time: clocks. Specifi…
- [fpgadesign.io #3 — Asynchronous Assertion, Synchronous De-assertion](https://fpgadesign.io/blog/fpgadesign-io-issue-3-resets.md) - 👋 Welcome back. The previous issue: the shift that's free until the amount stops being a constant. A few of you replied with the palindrome detector — nice work on the ones that scaled cleanly to 32 bits. This time, let's take a look at some nuances related to reset. The signal every design has, a…
- [fpgadesign.io #2 — The Shift that Costs Zero Logic Levels](https://fpgadesign.io/blog/2-the-shift-that-costs-zero-logic.md) - fpgadesign.io — Issue #2 RTL & FPGA design, explained the way interviews actually test it. 👋 Welcome back. Last issue: timing. Setup, hold, and why a hold violation is the one that should scare you. Several of you replied with your attempts at the skip-3 counter. Exactly what I hoped for. (Haven't…
- [fpgadesign.io #1: Setup & Hold, and Why One is Scarier](https://fpgadesign.io/blog/1-setup-and-hold-why-one-is-scarier.md) - Welcome to the first issue of the fpgadesign.io newsletter — or, for some of you, welcome back. A while ago I ran a newsletter on Substack, but a number of constraints meant I had to put it on hold. Now that the book is finally out, I'm restarting it — this time on my own platform at fpgadesign.io,…
- [Design Question: Counter that Skips Every Multiple of 3](https://fpgadesign.io/blog/design-skip3-counter.md) - Design a counter that starts at 1 and outputs a new value on every clock cycle, but it must never output a multiple of 3. The sequence looks like this: 1, 2, 4, 5, 7, 8, 10, 11, 13, 14 … — every third number is skipped. When most students first see this, they read it as a divisibility problem. The…
- [The Complete FPGA & RTL Interview Preparation Roadmap](https://fpgadesign.io/blog/the-complete-fpga-rtl-interview-preparation-roadmap.md)
- [Why Only the D Flip-Flop Exists as an FPGA Primitive](https://fpgadesign.io/blog/why-only-the-d-flip-flop-exists-as-an-fpga-primitive.md) - You studied four types of flip-flops in school. Only one survived into modern FPGAs — and the reason comes down to forbidden states, feedback topology, and what Static Timing Analysis needs to do its job.
- [~ vs ! in SystemVerilog: The Bug the Compiler Won't Catch](https://fpgadesign.io/blog/vs-in-systemverilog-the-bug-the-compiler-wont-catch.md) - On a single-bit signal, ~ and ! give the same result. On a multi-bit signal, they can give opposite answers — and the compiler won't warn you.
- [Reading a Timing Report: Why Your First Instinct Might Be Wrong](https://fpgadesign.io/blog/reading-a-timing-report-why-your-first-instinct-is-wrong.md) - Most engineers see a timing violation and immediately reach for pipelining. But the timing report is telling you exactly what the problem is — if you know how to read it.
- [XPMs: Beyond Instantiation and Inference](https://fpgadesign.io/blog/xpm.md) - Unlock efficient FPGA design with Xilinx Parameterizable Macros—flexible, reusable solutions for implementing on-chip memory, FIFOs, and reliable clock domain crossing using Vivado.
- ["Levels of Logic" in FPGA Timing Reports and Why It Matters?](https://fpgadesign.io/blog/levels-of-logic.md) - Explore the levels of logic in FPGA design, from high-level algorithms to register-transfer level (RTL), logic gates, and physical implementation. Understanding this concept is key for optimizing performance, area, and synthesis in FPGA projects.
- [Number Systems in Digital Design: Signed Arithmetic, Ones Complement and Twos Complement](https://fpgadesign.io/blog/number-systems.md) - Learn the key differences between signed magnitude, ones' complement, and two's complement—essential binary number systems for representing positive and negative integers in computers. Understand how each system handles sign bits, arithmetic, and zero representation.
- [Beyond Basic Gates: How Multiplexers Map to LUTs and the Power of Xilinx F7, F8 MUXes](https://fpgadesign.io/blog/f7-mux.md) - Understanding Xilinx UltraScale CLB architecture is necessary to fully harness the power of expansion multiplexers which can be cascaded at the output of LUTs.
- [Fixed-Point Representation: Mastering Precision in FPGA Design](https://fpgadesign.io/blog/fixed-point-representation-mastering-precision-in-fpga-design.md) - Understand the Qm.n Fixed Point Notation and how fractional numbers can be represented effectively in digital design.
- [Negative Hold Time Values in the Datasheet: Theory and Implications](https://fpgadesign.io/blog/negative-hold-time.md) - Understand what negative Hold times in datasheets mean for your digital designs. This concise guide explains why these values exist, their benefits for timing closure and high-speed circuits, and clarifies why negative Setup times don't apply.
- [Understanding Synthesis Directives](https://fpgadesign.io/blog/synthesis-directives.md) - Optimize your SystemVerilog RTL design for quality of synthesis results! Learn how synthesis directives (attributes) like KEEP and DONT_TOUCH provide crucial hints to your tools, enabling advanced optimization, timing closure, and efficient resource utilization in hardware design.
- [ASIC-Style Clock Gating in FPGAs](https://fpgadesign.io/blog/clock-gating.md) - How does ASIC-style Clock Gating translate to FPGA prototypes?
- [Understanding Clock Constrains](https://fpgadesign.io/blog/clock-constraints.md) - A complete overview starting with the basic timing constraints and building it up to the more advanced categories.
- [IOSTANDARDs in Xilinx FPGAs](https://fpgadesign.io/blog/iostandards.md) - What are they and Why are they needed in FPGA Design?
- [Endianness: The Byte Order You Didn't Know You Needed to Know](https://fpgadesign.io/blog/endianness.md) - Most engineers writing high-level software don't even care, but if you are engaged in low-level debugging at the hardware level, you definitely need to be aware of the the data "endianness" and how to handle it.
- [Design Question - Odd Parity Detector](https://fpgadesign.io/blog/odd-parity-detector.md) - How does Parity ensure data integrity? What are its limitations? Concept, Design Choices, FSM explained with SystemVerilog code
- [Design Question - Up-Down Counter with a Twist](https://fpgadesign.io/blog/up-down-counter.md) - Design Details, Explanation and Complete SystemVerilog RTL
- [Tri-State Buffers and Their Applications](https://fpgadesign.io/blog/tri-state-buffers.md) - How do complex microprocessor systems preserve the integrity of data buses?
- [Mealy and Moore Finite State Machines (FSMs)](https://fpgadesign.io/blog/mealy-moore-fsm.md) - Key Differences and Synthesis Implications
- [Packed vs Unpacked Arrays in SystemVerilog](https://fpgadesign.io/blog/packed-vs-unpacked-arrays-in-systemverilog.md) - Concepts, Use Cases, Syntax and Synthesis Considerations for using Packed vs Unpacked arrays in SystemVerilog
- [Design Question - Barrel Shifter](https://fpgadesign.io/blog/design-question-barrel-shifter.md) - What is a Barrel Shifter? How does it compare to a Shift Register? All concepts explained along with the SystemVerilog code for a 4-bit Barrel Shifter.
- [Advanced Topics in Static Timing Analysis](https://fpgadesign.io/blog/advanced-topics-in-static-timing-analysis.md) - Understanding Clock Skew, Clock Jitter and effects of additional pipelining on latency.
- [The Fundamentals of Static Timing Analysis in Digital Circuits](https://fpgadesign.io/blog/the-fundamentals-of-static-timing-analysis-in-digital-circuits.md) - Setup and Hold Time, Critical Paths and Other Key Concepts Explained
- [Design Question - Clock Dividers and Duty Cycle](https://fpgadesign.io/blog/design-question-clock-dividers-and-duty-cycle.md) - The ubiquitous Divide-by-3 Counter with 50% Duty Cycle and its siblings.
- [SystemVerilog .name and .* Notations](https://fpgadesign.io/blog/systemverilog-name-and-notations.md) - Do you use the .name and .* constructs in SystemVerilog? The advantages of using them and some more thoughts about streamlining your code.
- [Intricacies of Blocking vs Non-Blocking Assignment Statements in SystemVerilog](https://fpgadesign.io/blog/intricacies-of-blocking-vs-non-blocking-assignment-statements-in-systemverilog.md) - Have you really understood the nuances of Blocking vs Non-Blocking Assignment statements in SystemVerilog?
- [Designing with Xilinx Memory Primitives: Understanding Inference vs Instantiation](https://fpgadesign.io/blog/designing-with-xilinx-memory-primitives-understanding-inference-vs-instantiation.md) - When would you infer a memory primitive? What are the advantages of instantiating a memory module? There is a third alternative to inference vs instantiation. Do you know what it is?
- [An Introduction to Xilinx FPGA Memory Primitives](https://fpgadesign.io/blog/an-introduction-to-xilinx-fpga-memory-primitives.md) - Practical Insights into BlockRAM, Distributed RAM, and UltraRAM usage in your designs.
- [Gray Codes and Their Uses in Digital Design](https://fpgadesign.io/blog/gray-codes-and-their-uses-in-digital-design.md) - What are Gray Codes? Where are these codes used in Digital Design?
- [Control Sets Demystified](https://fpgadesign.io/blog/control-sets-demystified.md) - What are Control Sets in an FPGA Design? How do they affect the QoR of the final Placed and Routed Design?
- [Design Question - Pulse Generator](https://fpgadesign.io/blog/design-question-pulse-generator.md) - You are asked to design a module that generates a pulse, once every 32 clocks. How many ways can you implement the design? Would you do anything different if you are targeting a Xilinx UltraScale+ FPGA?
- [Rethinking Resets: Best Practices for FPGA Design](https://fpgadesign.io/blog/rethinking-resets-best-practices-for-fpga-design.md) - While designing an RTL module, most engineers do not even give a second thought to the reset signal. Every textbook on the subject touches upon the pros and cons of synchronous vs asynchronous resets. The texts generally focus on the correct syntax for inferring a synchronous or an asynchronous res…

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